The present invention relates generally to semiconductor memory devices, and in particular, the present invention relates to generating reference currents used in sensing data values in semiconductor flash memory devices.
Semiconductor memory devices are rapidly-accessible memory devices. In a semiconductor memory device, the time required for storing and retrieving information generally is independent of the physical location of the information within the memory device. Semiconductor memory devices typically store information in a large array of cells. A group of cells are electrically connected together by a bit line, or data line. An electrical signal is used to program a cell or cells.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes a non-volatile memory made up of floating-gate memory cells called flash memory. Computer applications use flash memory to store BIOS firmware. Peripheral devices such as printers store fonts and forms on flash memory. Digital cellular and wireless applications consume large quantities of flash memory. Portable applications such as digital cameras, audio recorders, personal digital assistants (PDAs) and test equipment also use flash memory as a medium to store data.
The threshold voltage of the floating-gate field effect transistor used in the floating-gate memory cell is indicative of its data value. The data value of the floating-gate memory cell is determined by sensing a current through the floating-gate transistor when a gate bias is applied to its control gate. The gate bias activates the transistor when the threshold voltage is indicative of a first programmed state and leaves the transistor substantially deactivated when the threshold voltage is indicative of a second programmed state. Typically, a charge stored on the floating gate varies the threshold voltage. However, as another example, the threshold voltage can be varied by fabricating the floating gate using a ferroelectric material and varying the polarization of the ferroelectric material.
Sensing a current indicative of a data value of a memory cell is typically facilitated with a reference current. The reference current can be used to develop a reference potential. This reference potential can be compared to a potential level developed by a target memory cell using a differential sensing device. Alternatively, the reference current can be combined with a sensed current as input to a single-ended sensing device. In this manner, the reference current is used to overcome any leakage of a target memory cell and reduce the likelihood of a false indication of an erased state of the target memory cell. To maintain consistency in sensing, the reference current is preferably proportional to the expected sensed current from an erased target cell across a variety of operating conditions.
Whether using differential or single-ended sensing, the reference current is typically developed using reference current generators based on a floating-gate field-effect transistor. There are typically many reference current generators in a memory device to maintain the load on each generator within acceptable power limits. Fabrication variability across a number of reference current generators can lead to large variations in the conductance of these transistors and the resulting reference currents. In order to generate reproducible reference currents across a memory device, it is generally desirable to trim each of these floating-gate transistors during testing of the memory device. This is a cumbersome operation.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative reference current generators, as well as memory devices and electronic systems making use of such reference current generators.
The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
Reference current generators are described for producing a reference current that is proportional to an expected sensed current of a target floating-gate memory cell in its conductive state. The reference current is compensated to track the expected sensed current across variations in both ambient temperature and supply voltage. The reference current generators are able to track the expected sensed current of a floating-gate memory cell without using a floating-gate transistor in the generator.
For one embodiment, the invention provides a reference current generator. The reference current generator includes a reference current path having a control node coupled to receive a reference current control signal and having an output for providing a reference current responsive to the reference current control signal. The reference current generator further includes a reference current control signal generator for generating the reference current control signal. The reference current control signal generator includes an output node coupled to the control node of the reference current path and a diode coupled between a first potential node and the output node of the reference current control signal generator. The first potential node is coupled to receive a first potential. The reference current generator further includes a resistive component coupled between a second potential node and the output node of the reference current control signal generator. The second potential node is coupled to receive a second potential.
For another embodiment, the invention provides a reference current generator. The reference current generator includes a reference current control signal generator for generating a reference current control signal on an output node. The reference current control signal generator includes a plurality of diode-connected p-channel field-effect transistors, each diode-connected p-channel field-effect transistor having a first source/drain region coupled to receive a first potential from a first potential node, a second source/drain region coupled to the output node of the reference current control signal generator, and a gate coupled to the output node of the reference current control signal generator. The reference current control signal generator further includes a first n-channel field-effect transistor having a first source/drain region coupled to the output node of the reference current control signal generator, a second source/drain region, and a gate coupled to receive a first control signal. The reference current control signal generator further includes a second n-channel field-effect transistor having a first source/drain region coupled to the second source/drain region of the first field-effect transistor, a second source/drain region, and a gate coupled to receive the first control signal. The reference current control signal generator still further includes a resistive component having an input coupled to the second source/drain region of the second field-effect transistor and an output coupled to receive a second potential from a second potential node. The resistive component includes a first resistive element coupled between the second source/drain region of the second field-effect transistor and the second potential node and a third n-channel field-effect transistor coupled between the first resistive element and the second potential node, the third n-channel field effect transistor having a gate coupled to receive the first control signal. The reference current generator further includes a reference current path having a p-channel field-effect transistor coupled between a third potential node and an output of the reference current path and having a gate coupled to receive the reference current control signal. Each p-channel field-effect transistor of the plurality of diode-connected p-channel field-effect transistors is sized to be substantially identical to the p-channel field-effect transistor of the reference current path.
For yet another embodiment, the invention provides a flash memory device. The memory device includes an array of floating-gate memory cells and a sensing device coupled for sensing a programmed state of a target floating-gate memory cell. The sensing device is selectively coupled to the target floating-gate memory cell through one or more pass circuits. The memory device further includes a reference current path having a control node coupled to receive a reference current control signal and an output coupled to provide a reference current to the sensing device. The reference current is inversely proportional to a value to the reference current control signal. The memory device further includes a reference current control signal generator for generating the reference current control signal, wherein the reference current control signal generator. The reference current control signal generator includes an output node coupled to the control node of the reference current path, a diode coupled between a first potential node and the output node of the reference current control signal generator, and a resistive component coupled between a second potential node and the output node of the reference current control signal generator. The first potential node is coupled to receive a first potential and the second potential node is coupled to receive a second potential lower than the first potential. The memory device further includes a circuit coupled between the diode and the resistive component circuit that mimics the resistance characteristics of the pass circuits.
The invention further provides memory devices and other apparatus of varying scope.